Abstract
Phase locked-loops (PLLs) are widely used in digital systems to generate well-timed clocks. Clock timing jitter is one of the most significant issues since any timing uncertainty limits the speed of digital systems. Scaling trends will shrink supply voltage and induce more switching noise from digital circuits to the power supply. The supply noise perturb the more sensitive blocks, especially for VCO in a PLL, and degrade PLL jitter performance. Therefore, it is desirable to design a VCO with good supply noise immunity. VCO tuning range and PLL output jitter are two common specifications for PLL design. This thesis proposes a design methodology for a supply-noise-insensitive PLL to meet VCO tuning range and PLL jitter requirements. The proposed methodology is general thus it is flexible for different applications. Based on the proposed design flow, a phase-locked loop (PLL) has been fabricated in 0.18-um / 1.8V CMOS technology. Chip area of the core circuit is 0:18mm2. Measurement results show that the PLL can generate clock signals ranging from 0.24GHz to 2.4GHz. Power consumption is about 18mW at 2.4GHz. Under quiet supply, PLL output long-term RMS jitter is about 1.3% UI over the tuning range. When a square wave noise is injected to VCO supply, PLL output clock has sensitivity 0.3%-clock period / 1%-VDD at 2.4GHz.