Abstract
The hot carrier degradation of 0.25µm process LDD n-MOSFETs with nitride spacer and sidewall buffer oxide (NOLDD) is characterized in detail. We find that the sidewall buffer oxide thickness intensely affects hot carrier reliability. A mechanism of multi-stage hot carrier degradation (linear gm degradation) is observed and only occurs in NOLDD device with thinner sidewall buffer oxide (100Å) under maximum substrate current Isubmax stressing condition, (Vg Vd /2). In the early stage (1ms~100s), the device degradation for Isubmax stressing condition performs “high-Vg-stressing-condition-like” (Vg=Vd) characteristic due to nitride spacer trapped electrons, which cannot be ignored any more and is mostly responsible for device degradation. After 100s, the second stage degradation performs more rapid power law gradient due to interface states generation compared with early stage. It implies that the electrons trapping mechanism predominates the early stage degradation, and then interface states generation competes against electrons trapping mechanism to dominate the second stage gm degradation while the sidewall buffer oxide is thinner. An examination of constant substrate current stressing suggests that the vertical electric field attracting hot hole near the drain edge is the main cause of interface states generation. Lifetime evaluation for devices with different buffer oxide thickness of 100Å and 150 Å is also carried out for comparison. While electrons are trapped in nitride spacer, the threshold voltage Vt extraction using gm-maximum exploration method in early stage hot carrier stress is proved to be an un-proper method to characterize device. Once a large amount of electrons trapped in nitride spacer, the drain series resistance increases, which transforms to reduce both transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. The threshold voltage Vt extracted with gm-maximum extrapolation method under this circumstance will become smaller and might be misjudged as trapped hole during the period of hot carrier stress. We consider the effect of series resistance on gm-maximum extrapolation method to find a relationship between the increased drain resistance and the decreased intercept gate voltage Vgsi. An extraction algorithm is derived, which establishes that the true threshold voltage of device remains unchanged under test during the early stage hot carrier stress.