Abstract
In this thesis, a switched-capacitor loop filter with phase detection function for PLL applications is proposed.In the first part, types of phase detectors are discussed and a sample-and-hold phase detector and frequency detector circuit is developed. It bases on switched-capacitor (SC) technique. It is a new architecture with frequency detection ability and is realized in UMC 0.18 1P6M Mixed-CMOS process.In the second part, a sample-and-hold loop filter is presented. It is found that the circuit used here is entire what we used in phase frequency detection (introduced in first part). The hardware saving property is high. For all SC circuits, reference feedthrough is a problem. Then the reference spur reduction technique is discussed. The total circuit consumes 1.134mW under 1.8 V supply voltage, and chip area is 0.162 (without buffer).In the third part behavior modeling of this SC phase frequency detection loop filter circuit is present. The locking behavior, spur performance is discussed here.A new architecture is proposed to ultimately reduce the cost of PLL without off-chip loop filter passive components. The area efficient is increased by hardware reuse.