Abstract
In this thesis, a CMOS image sensor (CIS) with ideal logarithmic response designed and fabricated in 0.35μm 1P4M n-well CMOS process is presented. A system level simulation environment that can simulate the images captured by an image sensor is also developed to help the designer to estimate how the components in a CMOS image sensor will affect the quality of output image. Then the designer can modify the characteristics of the components of the CMOS image sensor to get better output response.Moreover, a new concept of “multi-resolution” is proposed to modify the output response of a CMOS image sensor by modifying the transfer curve of the built-in Analog-to-Digital converter. After the modification, the output response of a CMOS image sensor approaches to an ideal logarithmic curve. Then the quality of the captured image can be improved under low illumination and, at the same time, the dynamic range of the CMOS image sensor will not be decreased at all.