Abstract
Leakage has become pronounced as technology shrinks to nanometer scale. A large portion of SOC power dissipation directly comes from on-die SRAM leakage power. Low-er rail-to-rail voltage is an effective method to reduce SRAM array leakage. For deep sub-micron technology, footer is a common technique to raise the source line of pull-down NMOS and reduce both sub-threshold leakage and gate leakage. Nevertheless, junction leakage still remains and becomes worse for nanometer technology. Therefore, header combined with floating bit-lines becomes a trend to lower SRAM cell bias because it can reduce junction leakage aggressively. In order to save wake up time and wake up power, we use a hybrid clamping structure composed of footer, header, and floating bit-lines due to simultaneous wake up behaviors. Besides, it should be carefully controlled to maintain sufficient cell stability, avoiding potential data loss. In this work, we propose a thermal aware leakage reduction scheme and also concern the data retention issue with PVT varia-tion tracking. A 32kb SRAM macro has been fabricated in 65nm bulk CMOS technology to verify the idea of this work. The measurement results demonstrate that the SRAM array leakage achieves above 80% reduction at high temperature. In addition, SRAM array lea-kage distribution becomes narrower in our scheme compared to original one.