Abstract
Datapath are usually on the critical path that determines the chip performance. We should take advantage of their regular and bit-slice structure to simplify the layout task and optimize the performance and area. Traditional placement tools do not treat datapath cells any different from random logic cell. Therefore, the layout quality is far from optimal. We propose a path model and a linear placement algorithm for datapath placement. We preserve the regularity of datapath structure for high-density layout. Blocks on the critical path are placed as tightly as possible to reduce the wire length and improve the timing. We also consider the routing congestion by carefully estimating the number of tracks needed. Experimental results are very promising.