Abstract
With the current trend in multi-functioning and minimizing the volume of electronic products, it is now necessary to shift from traditional two-dimensional packaging into three-dimensional (3-D) stacked packaging. In 3-D stacked packaging, the wafer-level-package (WLP) may be an effective solution because it completes the packaging operation directly on the wafer in flip chip manner and has good re-workability, which could reduce packaging costs in stacked packages and multi-chip modules. In this paper, a new packaging technology, chip-on-metal (COM) panel level package (PLP) with stacking and fan-out capabilities, is proposed. The concept of this package is to use the filler polymer material to pack the trench of the chip which is back-sided attached to the metallic chip carrier. Therefore, the solder bumps could be located on both the filler polymer and the chip surfaces by the redistribution lines and the pitch of the chip side is fanned-out. In addition, the soft polymer material could be treated as the stress buffer layer to improve the solder joint fatigue life. Moreover, the metallic chip carrier could be helpful in dissipating the generated heat from the chip. To assess the thermo-mechanical characteristic and thermal performance of the proposed PLP, the finite element analysis (FEA) in the board level is carried out. The parametric analysis of the COM PLP is studied to enhance its reliability characteristic and thermal performance. Furthermore, the factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information and interaction relationship between factors of the COM PLP. The results of this study showed that the predicted life cycles of solder joints in the PLP is found to possess outstanding performance. However, the stress concentration in via-through-holes (VTH) and redistribution traces may become another failure mechanism. In terms of thermal performance, the metallic chip carrier can rapidly dissipate the heat generated from the chip. Based on the reliability and thermal performance assessment, the design windows of the COM PLP and stacked PLP are established. Finally, this study is expected to become an important reference material for future research.