Abstract
Flash memory has been the mainstream technology in nonvolatile memories, applied in portable electronics for decades. Among the various types of flash memories, NAND flash memories provide one of the most competitive solutions in mass data-storage applications. Currently, NAND-flash-based solid-state disks are gradually replacing the conventional hard disks (HDs) because of their compact size and fast access rate. In high-density NAND flash devices, compact cells are subject to more stress and interferences, thereby degrading the reliability of these devices in their endurance and retention. During program and erase operations, electrical stress of the tunnel oxide generates defects, leading to a reduced lifetime during cycling endurance. The trapped charge influences the potential energy between the floating gate and substrate and reduces the programming/erasing efficiency during operations. As trapped charge accumulates in the tunnel oxide layer, programming characteristics can drastically shift. Furthermore, these stress-induced defects worsen the data retention characteristics as a result of charge lost through trap-assisted tunneling which can lead to significant increase in error bits after program/erase (P/E) cycling. Prior studies revealed that the cycling time and operation temperature both affect the charge-detrapping process. This study first investigates the effect of these operational parameters on the error bit rate across an array during P/E cycling endurance tests. Then, based on the experimental results, a new operational scheme is proposed to promote the defect recovery process, thus effectively enhancing the cycling and retention lifetime in gigabit MLC NAND flash memories.