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分數型除頻器設計及其頻率合成器應用
Thesis

分數型除頻器設計及其頻率合成器應用

沈孟緯
Masters, National Tsing Hua University
2004

Abstract

鎖相迴路頻率合成器除頻器 CMOSPLLFrequency synthesizerDivider
In this thesis, a 5 GHz frequency synthesizer and a BFSK transmitter are proposed.In the rst part, a high operating frequency and low power programmable divider is developedfirst, which uses cascade 9-stage divider-by-2/3 cell to achieve the capability that switches divisor arbitrarily from 512 to 1023. Based on this divider, a 5.2 ~ 5.8 GHz fractional-N frequency synthesizer is realized in UMC 0.18 um 1P6M RF-CMOS process. Except the multi-modulus divider, this frequency synthesizer includes a voltage control oscillator, all digital 3rd-order singleloop sigma-delta modulator, phase-frequency detector and charge pump, and a linear regulator.The synthesizer consumes 25.0 mW under 1.8 V supply voltage, and chip area is 2.32 mm.In the second part, a low power BFSK transmitter for capsule endoscope applications is presented. The transmitter is realized by a phase locked loop with a dual-loop modulation, which includes a linear regulator and an efciency PA itself. For a 1.85V regulated power supply, the transmitter power consumptions are 3.83mW, with -23.82 dBm output power and maximum 2 Mbps data rate. The transmitter IC is implemented in TSMC 0.35 um CMOS process and total area is 3.47 mm.

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