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分離閘快閃記憶體之新型位元線控制多階編程操作研究
Thesis

分離閘快閃記憶體之新型位元線控制多階編程操作研究

翁偉哲
Masters, 國立清華大學, 電機工程學系
1998

Abstract

快閃記憶體 分離閘快閃記憶體 多階層寫入操作 Flash Memory Split Gate Flash Memory Multi-level Programming Scheme
Flash memories belong to the family of non-volatile memories, the first conceptual MIMIS device structure was proposed by D. Kahng and S. M. Sze in 1967. Thank the advancement in semiconductor manufacturing technology, the cost reduction makes Flash memories a superstar in the coming era. The key to compete with other memories is to move toward high density, low power consumption, low cost and high efficiency. The first idea flashes when talking about Flash memories should be the well-known stacked-gate devices. Due to the small size and simple process, it becomes popular in this field. However, there is no denying that another split-gate structure is also influential This thesis will be dedicated to the study of split-gate Flash memories utilizing Source-side Injection operation. Comparing with the stacked-gate Flash memories, it has advantages of high injection efficiency, anti-radiation and over-erase immunity, though at price of larger device area and more complex manufacturing process. This thesis discusses the multi-level programming method to solve the fatal disadvantage of low-density for split-gate Flash memory. After evaluating the device characteristics and surveying the published literatures, the author starts from the ramp-up voltage operation, which has attracted many researchers’ attention. Based on the understanding of operating mechanisms, possible multi-level programming schemes are proposed. Considering the trouble will be encountered by each method, the author finally grades these schemes for adaptability.

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