Abstract
In the top-down design flow, the RTL(Register Transfer Level) design is one of the most widely used design representations for Digital IC's. Therefore, it is important to ensure that the design functionality is correct at this level. Recently, the ASIC design is more and more complex and the functional verification takes more and more efforts accordingly. Very often, we need to debug an RTL code that has been proven incorrect. In this thesis, we present an RTL simulation platform based on Control Data Flow Graph (CDFG). Upon this platform, RTL diagnosis or code coverage analysis can be performed more efficiently in the future. The proposed simulation mechanism is a cycle-based behavior simulation.It incorporates both a parse tree and a CDFG to represent the RTL design. The parse tree represents the code structure, while the CDFG represents how the control signals interact with the data flow. Based on such a dual presentation, we will be able to perform simulation using the path enumeration technique. In this technique, we compute the value of each register and output signals by evaluating the computational path under execution for each clock cycle. As an experiment, we tested this program using a Greatest Common Divisor design. In addition to producing correct output responses and execution traces, the program can also report all computational paths to aid the subsequent design debugging process and/or testbench generation process.