Abstract
This thesis presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC) for wireless sensor network. The proposed ADC operates at ultra-low supply voltage from 0.4V to 0.7V to save power consumption. The hybrid architecture is proposed to reduce the total amount of capacitance and relieve requirement of comparator, and the ADC is composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit redundancy by Vernier delay structure. The prototype was fabricated using 90nm 1P9M CMOS technology and core area is only 120×340μm2. At 0.4-to-0.7V supply and 250KS/s-to-4MS/s sampling rate, the ADC achieves SNDR from 53.7 to 54.8dB corresponding ENOB from 8.63 to 8.81 at Nyquist-rate input and consumes 0.2-to-9.3 W power consumption, resulting in a figure of merit (FOM) from 2.02-to 5.16 fJ /conversion-step.