Abstract
In this paper we present both fully parallel and bit-oriented architectures for the digital Finite Impulse Response (FIR) filters with adaptive coefficients. Instead of using multipliers, the FIR operation is regarded as the summation of a larger number of operands. Our architecture utilizes a new compressor called 6-to-2 compressor, which converts six data bits of equal weights into a two-digit representation. Using such a compressor as the basic building block, an FIR can be implemented as an efficient and regular structure that lends itself to automation. Experiments show the Power-Delay-Area (PDA) products of the proposed fully parallel and bit-oriented FIR filters are only 43.0% and 5.19% compared with the transposed form.