Abstract
In the phase-locked loop (PLL) design, the locking time and the jitter depend on the loop bandwidth. Increasing the loop bandwidth of the PLL can reduce the locking time, but also increase the jitter. In order to gain the fast locking time and the low jitter, the adaptive PLL concept which uses dynamic bandwidth adjustment is presented. Therefore, the loop bandwidth switch mechanism is required to monitor the PLL locking status and adjust the loop bandwidth. In this thesis, the dual-edge phase-frequency (DE-PFD) detector is well integrated in our adaptive PLL. The DE-PFD speeds up the locking time by detecting the phase difference between reference clock signal and PLL’s feedback signal of the divider circuit in both rising edge and falling edge simultaneously. Meanwhile, the proposed signal generated from the DE-PFD can control the charge pump to charge/discharge low pass filter to switch the loop bandwidth. Compared with the conventional adaptive PLL, the locking detector using DE-PFD save the hardware overhead and switch the bandwidth smoothly. However, the DE-PFD not only speeds up the locking time but also increases the noise of the PLL. Therefore, the DE-PFD is switched to the single-edge PFD to decrease the noise when the PLL is locked. The proposed adaptive PLL combines the dynamic bandwidth concept with the DE-PFD to speed up the locking time. It can make a decision of the switch timing easily by processing the signals of the DE-PFD with the bandwidth control unit (BCU). The locking status detection algorithm of the proposed circuit is simple to be implemented and also can avoid the uncertainty issue from process variation. With the adaptive bandwidth and the dual-edge PFD, the time improvement is 59.2% by simulation.