Abstract
With the advantages of at-speed testing, functional mode operation and low area overhead, functional self-test approach is wildly adopted nowadays for delay fault testing. However, modern designs will make this approach hard to apply due to large gate counts and complex functionality. Thus, a modified functional test flow is proposed by this paper to test processors and could be extended to ASICs. This flow includes circuit partition, constraints extraction, pattern generation and back-trace. Each part of the proposed flow is more automatic and effective than other method. The experiment result is demonstrated by testing Parwan processor. And the result showed is good by the proposed method.