Abstract
Flash memory is widely used in many applications nowadays. Theuse of commodity and embedded Flash memories are growing rapidly as the demand of 3C products increases, especially for the battery-powered devices and other low power devices. Flash memory can be programmed or erased electrically on-line, and retains its stored data for a long time, so it is very suitable for mass storage. The larger the Flash memories we produced, the higher the cost in test and diagnosis in order to guarantee their yield. Therefore, the testing of Flash memory is an important issue, especially for reducing the test cost and improving the yield for mass production. In this thesis, we propose a flexible BIST circuit design for Flash memory which can reduce the test time and the diagnostic data shift-out cycles. This is done by performing parallel programming/erasing and parallel shift-out mechanism with error index encoding. We also develop a low-cost prototyping diagnosis system by FPGA, and verify our BIST design with real commercial products. This FPGA-based system can be used to diagnose the Flash memory, eliminating the need for expensive ATE, thus reducing the test cost. Our experimental results show that the BIST scheme with small area overhead is suitable for Flash memory testing. The area overhead of our BIST circuit is about 0.5% for a commodity 264Mb AND type stand-alone Flash memory. The total test time is reduced to 64.4\% compared with the original test time. The parallel shift-out mechanism reduces the shift-out cycles (in diagnosis mode) to 20% compared with the original shift-out cycles. We also propose a device protection mechanism which prevents the internal high voltage generator from being damaged by the noise on reset pin that forces the BIST to reset.