Abstract
Dynamic PLAs which are built of the NOR-NOR structure have been very popular in high performance design because of their high speed and predictable routing delay. However, the NOR-NOR structure incurs high switching activity in product lines and thus results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. Since there are many candidates for the super product lines, we have developed a CAD algorithm based on the maximum weighted matching to find optimal solution. In addition, the line reordering method is applied to further reduce the power consumption. We have performed experiments on a large set of MCNC benchmark circuits. Our experimental results not only show significant reduction in power but also the delay. On the average, the power consumption can be saved 54.86% and the delay can be improved 17.12%.