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Thesis
十位元每秒取樣四千萬次管線式類比數位轉換器之實現
周育諒
Masters, 國立清華大學, 電機工程學系所
2017
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Abstract
類比數位轉換器
管線式
1.5-bit/stage
疊接式米勒補償
ADC
pipelined
1.5-bit/stage
caccode miller compensation
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Title
十位元每秒取樣四千萬次管線式類比數位轉換器之實現
Translated title
十位元每秒取樣四千萬次管線式類比數位轉換器之實現
Creators
周育諒
Contributors
鄭桂忠 (Advisor)
Awarding Institution
國立清華大學, 電機工程學系所; Masters
Theses and Dissertations
Masters, 國立清華大學, 電機工程學系所
Language
Traditional Chinese
Resource Type
Thesis
Date published
2017
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