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半導體元件測試排程模式之研究
Thesis

半導體元件測試排程模式之研究

吳吉政
Masters, National Tsing Hua University
2000

Abstract

半導體元件測試排程機台組合遺傳演算法甘特圖 Semiconductor Final TestingSchedulingMachine ConfigurationGenetic AlgorithmGannt Chart
Recently, using computers to assist in detailed scheduling becomes more feasible and popular due to high improvement of information technique and operation research. It is very difficult to design an effective and efficient scheduling method for semiconductor manufacturing with complex manufacturing flow. Some researches have focus on scheduling and dispatching for Front-End of semiconductor manufacturing. However, little research has been done for designing practical scheduling methods of Back-End of semiconductor manufacturing. This research considers manufacturing dynamics, jobs recirculation, limited resource, optimized machine configuration, and that the same product can be tested on different types of machines with non-identical efficiency and constructs an optimal mathematical model for semiconductor final testing. Besides, for practical purpose, this research also develops a heuristic and a quality-improved genetic algorithm with procedures graphically representing schedules based on Gannt charts. After simulations and experiments, we find that the proposed heuristic and genetic algorithm perform better than dispatching rule-based heuristics.

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