Abstract
In this thesis, we present an implementation of a bit-level systolic array RSA cryptography core, based on a modified Montgomery's algorithm. The improved Montgomery's algorithm guarantees that the partial products fall within the range [0, 2^{n+1}) and thus post adjustment is removed. It also results in a better architecture and performance. Based on a standard procedure, we map the algorithm to a systolic array. Since it is a systolic array, there is no global line and we come up with a design that has a very short critical path. For testing, it is regular but highly sequential. We use ATPG tools and the full-scan approach to solve the testing problem. A testable RSA cryptography core has been implemented. The time to finish a modular exponentiation operation is about 2n^2 clock cycles, where n is the word length. The utilization ratio of the systolic array is 100% by interleaving the squares and multiplications in the modular exponentiation operation. The testing time is about 1.6ms for a 512-bit RSA core. Furthermore, regularity, local interconnection, and modularity make the design suitable for VLSI implementation. With the Avant! 0.35um standard cell library, we have implemented a 512-bit testable RSA cryptography chip. After post-layout simulation, the baud rate of the chip is about 386$K$. This core can be easily integrated into any cryptosystem.