Abstract
A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus it need to be identified during the manufacturing test or functional test in order to improve the yield and maintain the reliability. In this thesis, we present a novel test method to determine if a clock network has any small delay fault. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 40ps through outlier analysis, while locating the FFs affected by the fault in the meantime. Furthermore, the overall test process does not involve loading of test patterns and thus can be conducted very easily by a Built-In Self-Test (BIST) controller when it needed.