Abstract
Consider the possibility of specializing a microprocessor instruction set so as to optimize its performances for a given class of applications. Such an approach combines the time efficiency of application-specific functional units with the flexibility of programmable devices. In this thesis, we propose a reconfigurable VLIW architecture named "Practi-Tecture," which consists of a general VLIW core and a reconfigurable datapath, totally up to eleven-way issue with two ALU unit, for general arithmetic, bit-wise, saturation, compare operations, two MAC units, for multiply, multiply-accumulate operation, one BAU unit for simple arithmetic, branching and SIMD style operation, one auxiliary unit for simple arithmetic, predicate register movement and SIMD style operation, three load/store units for memory access and register movement operation, and two reconfigurable functional units(RFU) for customized datapath instructions. In the VLIW architecture, the pipeline stage design of functional units could affect the overall system performance, such as memory access latency, branch latency and other operations latency. The detailed design the of pipeline stage of each functional unit will be discussed in this thesis. We also discuss the design of our customized datapath instructions such that the reconfigurable part is not only a co-processor but also simultaneously executes operations with VLIW core. The assembly language and instruction encoding scheme will also be presented in this thesis. According to this architecture design, the resource contraints will also appear on assembly language programming. The experiment is done with hand-coded assembly on DSPStone and other DSP relative application. In our experiments, we compare the performance on execution cycles and code size with TIC6X DSP family, the experiments show average 36.6% improvement on performance and average 36.67% improvement on code size.