Abstract
DRAM timing parameter testing has always been considered a complex and time-consuming process. This thesis presents a systematic approach to analysis of the synchronous DRAM (SDRAM) circuit and classification of all SDRAM delay failure modes. We show that certain failure modes that are directly linked to existing timing parameters are not covered by traditional functional fault models. Therefore, the current practice in the industry is to test the critical timing parameters separately, in addition to testing the functional faults. In this thesis four delay fault models are proposed to cover these critical timing parameters. The activation and observation conditions for these delay faults are discussed and thus theMarch test solution is presented. The test can further be supported by our proposed programmable BIST, which the area overhead is considered 15.9% compared to conventional BIST, less than 1% compared to the memory die size. By only testing these four types of delay faults, we can verify the correctness of timing specifications without traditional complex patterns.