Abstract
Floating-gate device has been widely used in many commercial nonvolatile memorie products, such as EPROM, EEPROM, flash memory, etc. Due to its good compatibility with standard CMOS process, floating gate device has been treated in some studies as an analog circuit element in the analog circuit design since the 90's. As the technology moves into deep-submicron processes, more attention needs to be paid to utilize floating gate device as an analog element. This study proposes a floating gate device constructed with three P-channel MOSFETs fabricated in a single poly 0.18μm CMOS process. The device is programmed by ion impact hot electron, and erased by FN tunneling. Experimental data of electrical characteristics during programming and erasing, device endurance, and data retention is given in this study. In order to simulate the characteristics of the floating device by SPICE in circuit design, this study build up a SPICE compatible effective circuit model of the floating gate device, by building up the hot electron injection current model and the FN tunneling current model. Experimental data is compared with simulation results to verify the accuracy of this effective circuit model. This study concludes with two novel application circuits of the floating gate device. To deal with many restrictions of traditional translinear circuits in standard CMOS process, this study proposes to utilize floating device as a solution. By modifying the current-voltage relationship of the transistor, reduction of errors from the translinear circuit are expected. Experimental data of the proposed circuit is given in this study to verify the new solution of translinear circuit design. Finally, this study presents a novel design for a DAC using floating-gate MOS transistors. This approach takes the classical scaled transistor DAC techniques, where we scale our transistors by programming each transistor’s floating-gate charge instead of W/L ratios. The programming eliminates device mismatch issues on DAC performance, and greatly reduces its size. Experimental data of the proposed circuit is also given in this study.