Abstract
As the traffic load increases, System-on-Chip faces the performance bottleneck in the communication architecture. Network-on-chip is a popular solution. It uses many inventions from wide-area networks and on-board multi-processor communication structures, and shrinks their scale to the chip level. There are many system-level simulators for Network-on-chip design. This paper presents our work, Nocsep, standing for ―Network-On-Chip-centric System Exploration Platform‖. It provides (a) an on-chip system framework with which we can build up the entire on-chip traffic across network layers, (b) the multi-abstraction-level components for each network layer to reduce the coding effort for a new NoC design, and (c) a system performance estimation environment highly compatible to any traditional SystemC designs with some improved features. In Nocsep, the design space of an NoC-centric system is clearly divided. One system is divided into many layers. One layer is divided into many components. One component is divided into many abstraction levels and one abstraction level is divided into many stages. Each stage is estimated in the latency model which has many latency parameters. Therefore we can claim that Nocsep design space is much larger than other existent NoC simulators. Most importantly, all the Nocsep models are implemented in practice thoroughly in SystemC codes and some demonstrations are discussed at the end of this paper.