Abstract
With the advancement of process technologies, the dimension of BEoL (Back End of the Production Line) interconnect has become smaller and smaller. Therefore, it will reveal many issues and challenges unceasingly that need to be concerned than before. One of them is on-chip interconnect induced issue, such as parasitic capacitance, parasitic resistance and parasitic inductance, they are attentive now. In the meanwhile, parasitic capacitance makes interconnect consume more time in transmitting signal than transistor, this situation results in an unexpected performance to the whole chip. Therefore, we need to model the interconnect capacitance accurately; then we can help IC designer to design their circuits and estimate the RC delay much precisely. Nowadays, the efficient way is to use computer software to massively generate correct test structures and collect the results to analyze them. Hence, these software need to be verify their accuracy when the process technologies make progress gradually. In this paper, we develop a software package to generate more than 8 thousand (categorized into 8 types) test structure input files automatically and use them to verify two pieces of electromagnetic field simulation software, Clever and Raphael. Although we don’t have silicon data of these test structures, we can still compare the capacitance results simulated from Clever and Raphael to explain whether they are reasonable or not. Simultaneously, we consider the process variation and lithography effect, they cause the shape of interconnect and via look like a trapezoid and a cone respectively. Therefore, we modify the shape of our test structures much more close to realistic cases. By adopting this more comprehensive description as input files, we can examine the validity and accuracy of field simulation software. Finally, we discuss the accuracy, execution resources and user-friendly between Clever and Raphael to help IC designers to design their circuits.