Abstract
Clock signal is the most important part in synchronous circuit and a good circuit design must have a robust clock signal. Clock skew and clock jitter are the most critical factors whether the design meets the specifications or not.Therefore, many devote to inventing some routing algorithms attempting to reduce the clock skew or clock jitter. In the past, we only considered the effects of resistance and capacitance. Those algorithms can generally solve the clock skew and clock jitter problems. However, with the advance of silicon process and giga-hertz-level frequency, the effect of inductance has become as important as that of resistance, or even greater than the resistance. For crosstalk effect, the inductance becomes very important, especially in the fast-switching signals like clock signals. Furthermore, the chip may catch the wrong signals (false switch) if we cannot extract parasitic resistance, capacitance, inductance and simulate them accurately. But now, the commercial software usually ignores the effect of inductance. It should be said that they do not know how to analyze the inductance, so they pretend that they can’t see the inductance. As a result, it is likely to misjudge the value of clock skew, decrease the chip yield and increase uncertainties. In view of this, we develop novel software: ClockHenry. It’s convenient to extract parasitic resistance, capacitance and inductance in the SPICE netlist for clock tree designers.Besides, we advocate using a new clock tree routing strategy: clock shield routing for clock nets. The clock nets should be optimized based on EM waves in order to decrease the clock skew due to the effect of inductance. After adopting the clock shield routing approach, there is still need to judge the clock skew by modeling the effect of inductance accurately. In this thesis, I will enumerate five kinds of floorplan architectures and route the clock trees with a variety of comprehensive styles of clock tree routing strategies. We route block-level clock lines with traditional and asymmetric clock tree routing approach and then we route global clock lines with full-custom symmetric H-tree or with exact zero skew clock routing algorithm proposed by NTHU Professor Ren-song Tsay. Then, we analyze quantitatively the electric properties according to our comprehensive sets of clock design ideas.Furthermore, the process parameters may change due to uncertain factors such as environmental variations, different instruments, etc. So how to analyze and simulate inevitable process variations efficiently and accurately is also very important. We know that process variations can be divided into three categories namely (a) device, (b) system and (c) interconnect process variations from public domain literature [12]. We will focus on interconnect and system process variations. The main variable parameters are metal width, metal thickness, interlayer dielectric thickness (ILD thickness) and power supply voltage. Using interconnect and system process variations, we can quantify the electric properties between different clock tree routing methodologies along with our timing analysis method. In this way, we deomonstrate the clock shield routing strategy is less sensitive to process variations compared with traditional clock routing strategy.However, the clock shield routing strategy is not perfect since it has some disadvantages. The most important two are silicon area and average clock power dissipation penalties. In this thesis, we describe representative clock shield routing approaches along with the corresponding area and average clock power dissipation penalties, which are in the range of.Finally, we experiment on the clock skew performance between our SoC clock routing and Astro clock routing approaches. We observe that Synopsys Astro versions from CIC can only give designers the resistance and capacitance tables from the foundries. Therefore, the academia in Taiwan must add the effect of inductance into consideration by extra software, which is implemented in our lab and is called ClockHenry that can extract resistance, capacitance and inductance tables to supersede CIC tables available. We need Clock Henry to facilitate the overall simulation of SoC clock trees. Because the foundations of H-tree or exact zero skew clock routing algorithm are based on the same resistance and capacitance per unit length. And these concepts coincide with clock lines after shielding. So clock skew can be approved after adopting clock shield routing algorithm. However, the foundation of Astro clock routing approach is to balance delay time of each clock path. How to determine the number and location of clock buffers is according to the environment of traditional clock trees. The improvement of clock skew may not be very good after adopting clock shield routing algorithm.Keywords: synchronous circuits, clock skew, clock jitter, high-frequency, partial inductance, loop inductance, inductance matrix, on-chip inductance modeling, shield, SoC clock tree, RF clock tree, H-tree, exact zero skew clock routing algorithm, clock buffer insertion, setup time violation, hold time violation, even (odd, common) mode, average clock power dissipation, interconnect variation, power supply voltage variation, area penalty, Synopsys Astro, distributed model, DFM.