Abstract
In the past two decades, flash memory has played an important role in the storage market, and NAND flash memory has become the best solution for massive storage due to its low cost and high density. However, as the medium CMOS technology progresses, the size of a memory cell becomes smaller and smaller, and the developers face with severe challenges in terms of memory durability, reliability, and device lifetime, when experience frequent erasing and programming during oper-ation. In programming and erasing cycle tests, defects are created on the channel oxide film. These defects occur at the interface between the oxide layer and the substrate which converse to phase noise that affects the per-formance of memory array. The above behavior caused the capture and re-lease of electrons, which in turn changed the current of the channel, lead-ing to random telegraph noise. Also, as the chip size shrinks, signal to noise ratio decreases which cause additional challenges in readout circuit design much more difficult. Therefore, analysis on the influence of process and experiment on random telegraph noise is very important. With the miniaturization of devices, the impact of random telegraph noise cannot be ignored. Therefore, this study employed 1X nanometer NAND flash memory as test subject, and discuss under the circumstances which one can induced random telegraph noise the most easily. Moreover, the effects of different manufacturing processes on RTN on 2D NAND flash memory arrays.