Abstract
For deep submicron VLSI technology designs,interconnect delay has become the critical major factor for the circuit performance in VLSI systems.Wire sizing, buffer insertion and driver sizing are the most effective techniques to improve the interconnect delay.Among them, buffer insertion particularly is a very effective and powerful method.With the rapid growth of the IC technology, it is expected that a single chip may have many buffers inserted.Hence, a systematic buffer planning method is needed.In this thesis, we will propose an efficient algorithm for global routing and buffer insertion in building block layout.First, initial routes of all nets are performed taken the congestions and distance into consideration.Based on the initial routing and timing requirements of all nets, buffer blocks are allocated gradually.Experimental results show that our algorithm is very fast and efficient and needs less area overhead as compared to [6] . Moreover, our algorithm guarantees 100% nets routing completion.