Logo image
在多核心數位訊號處理器上論減縮 H.264 之4×4畫面內亮度預測程式碼
Thesis

在多核心數位訊號處理器上論減縮 H.264 之4×4畫面內亮度預測程式碼

Chen,Yan-Fu
Masters, 國立清華大學, 資訊工程學系
2008

Abstract

多核心 省電 H.264 程式碼減縮 數位訊號處理器 Multicore power saving H.264 code size reduction DSP
As the latest international video coding standard, H.264 is gaining importance not only on desktop computers but also on handheld devices. For handheld devices, power consumption of the system is of ultimate importance, which needs to be addressed at every layer of the system design. At the application layer, the code size affects the memory hierarchy behavior, which in turn affects the system power performance. In this thesis, we consider the power consumption of H.264 running on handheld devices using multicore DSP processors, focusing particularly on power saving through code reduction. We use the multiple intra-mode prediction as an example. There are nine optional prediction modes for each 4 × 4 intra luma sub-macroblock in H.264, which result in nine separate routines. We examine the access patterns of the modes and propose a general scheme that replaces eight of the nine routines with one. This dramatically reduces the code size and the resultant power consumption. We implemented the code on PACDSP, resulting in a 20% reduction of the code size with negligible performance degradation.

Metrics

1 Record Views

Details

Logo image