Abstract
In this thesis, we study a floorplanning problem for die-stacking System-in-Package (SiP) designs in which the wire bonding method is used to connect signals between different dies. We present an approach which sequentially determines a floorplan for each die from bottom to top such that the generated floorplan has minimal on-chip wirelength and satisfies given temperature and fixed-outline constraints. To find such a floorplan for each die, we modify an existing simulated annealing based fixed-outline floorplanner by adding several temperature-aware schemes. The experimental results are provided to show the efficiency and effectiveness of our approach. To our best knowledge, our work is the first one to give a promising floorplanning approach to die-stacking SiP designs.