Abstract
In this dissertation, QoS (quality of service) control schemes for output-queuing ATM switching systems and fault-tolerant mechanisms for ATM switches are studied. Based on these studies, we proposed a high-performance ATM switching System that can provide QoS control for multiple QoS classes and be able to tolerate a lot of switching element failures. It is well-known that ATM (Asynchronous Transfer Mode) switching technology has been playing an important role in the B-ISDN (Broadband Integrated Services Networks) which accommodates more and more services requiring to transmit hybrid types of media such as text, image, video and audio data. Since different services may have different quality requirements such as cell delay, cell loss ratio and cell delay variation, it is very important to have some cost-effective QoS control scheme that can meet requirements of all granted connections in the switch. Whether the requirements of a connection can be guaranteed depends on the buffer management and service policy of the switching system. Since both buffer management and service policy can affect the cell delay, cell loss ratio and cell delay variation of a connection, it is very hard to find a subtle scheme that can support services with different requirements on cell delay, cell loss ratio and cell delay variation. In the proposed ATM switch, a simple and cost-effective QoS control scheme is provided with each output port of the switch. This generalized QoS control scheme integrates the partial buffer sharing buffer management mechanism and the weighted-round-robun service policy to support services with different cell-delay and cell-loss requirements. We have analyzed the queueing model of the proposed QoS control scheme and derived the cell delay and cell loss ratio performance for four QoS classes. Our results are compared to those of another QoS control scheme that employs dedicated buffer for each QoS class. The comparison result shows that our scheme takes less buffer space to achieve the same performance.Fault-tolerance is another important issue in the design of an ATM switch. The high-bandwidth attribute of an ATM switch allows more connections to be connected in the switch at the same time. However, this implies a bigger disaster may be brought if the switch suddenly breaks down. To become fault-tolerant, there must exist more than two paths between any input and any output of the switch. Once some switching elements malfunction, the switch must reconfigure the switch in a certain way such that each cell can still be successfully routed to its destination via alternative paths that can bypass malfunctioned switching elements. The fault-tolerant switch proposed in the dissertation is constructed by applying a simple reconfiguration scheme to a high-performance switch called Shuffleout switch. We have analyzed the throughput, number of redundant paths and the survival probability of the proposed re-configurable Shuffleout switch. The evaluation results show that our reconfiguration scheme can promote the reliability of the Shuffleout switch to a great extent and reduce the degree of performance degradation when some components of the switch are malfunctioned.