Abstract
Due to the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The IEEE 1500 is provided to test functionality of each core in SOC but dose not verify its timing specifications. In this thesis, a delay fault test architecture that consists of modified wrapper based on IEEE 1500, a delay-test-aware clock controller and the modified TAP controller are presented. The delay-test-aware clock controller can generate the desired clock pulse for delay fault timing specification. Then, the test sequence is controlled by the modified TAP controller. The simulation results show successful delay fault testing application to a Crypto Processor with satisfying test quality and accuracy.