Abstract
In this paper, a 1.2V low voltage sop-based sample-and-hold circuit was proposed. In this architecture, we propose a new rail-to-rail sample-and-hold circuit instead of Dai’s SOP architecture which can be used in low voltage application. Our SOP has higher sampling rate and we use double sampling technique to increase sampling rate and still maintain circuit linearity. Our proposed circuit achieved higher sampling rate and need less transistors, but has larger capacitor area cost and still has charge injection error. We compared our circuit with other low-voltage sample-and-hold with rail-to-rail output circuit. We can see that our circuit has higher sampling rate.