Abstract
Dynamic Voltage-Frequency Scaling (DVFS) has been proposed for a good balance between power and performance in processor design. Various DVFS methods are now applied to modern processor designs. These techniques sometimes make processors and cache operate at lower supplying voltage for energy saving. But the scaled-down supplying voltage greatly decreases the reliability of cache at the same time. To address this issue, we propose a cache-utilization based DVFS mechanism utilizing 7T/14T cache architecture [1] for reliability enhancements. In our method, under ultra-low voltage, the cache system can still operate in a reliable state. Di fferent from conventional DVFS, in order to combine perfectly with 7T/14T cache architecture, we consider not only CPI behaviors but also a new metric -- cache utilization, which we use to estimate the effectiveness of cache capacity. A set of experiments to examine our method are conducted in three degrees: reliability, power, and performance. The results show that compared to the online learning DVFS method [2] using safe supply voltage, reliability by our method improves in average from 0.246 ECC errors per day to 0.113, with 2.2% energy reduction and 5.5% speed-up in performance. Moreover, compared to the online learning DVFS method using ultra-low voltage, reliability by our method improves in average from 522.85 ECC errors per day to 0.113, and 1.5% reduction in energy and 5.5% speed-up in performance.