Abstract
As improvement of System-on-Chip technology, multi-core processors are becoming more and more important. Efficient and robust data transferring is one of the most critical and complex issues to be considered, especially when designing multi-core systems. This thesis presents an RTL implementation of mesh-based multi-core architecture containing 16 processing elements (PEs). Our platform provides 1) robust data transmission between PEs, 2) ability to execute realistic parallel programs, 3) approaches to profiling system bottlenecks, 4) cross-verification with ESL (Electronic System Level) design, and 5) physical characteristics such as power, energy and frequency as a feedback to ESL design. Each PE has single processor and a Transmission Unit (TU). The TU is composed of a proposed PE-to-PE Core and a modified DMA core. Data transmission between PEs is assisted by the proposed PE-to-PE Core, instead of accessing remote memory directly due to system stability. And the DMA core is used to move data between the local memory in a PE and the external memory controller with an OCP interface. In addition, the Transmission Unit is software driven, so that a Low-Level Communication (LLC) library is designed and proposed. The LLC library provides controls of the Transmission Unit. Furthermore, the LLC library supports a software protocol to avoid unexpected sequence errors for software developers. Based on LLC software protocol, message passing libraries such as the iLib library can be implemented to evaluate the system performance by porting realistic parallel programs. Evaluating system performance usually takes millions of cycles. Complicated and realistic parallel programs such as Odd-Even Sort and JPEG encoding are ported to this platform. And the application features such as total cycle count, memory behaviors and communication cycle count can be collected. Through these test cases, we can find out bottlenecks in multi-core platforms, and the feedback benefits platforms working at high abstraction level, or so called Electronic System Level (ESL) such as SystemC. The architecture exploration can be progressed in the SystemC platform first, and the corresponding adjustments then are provided for the RTL platform. Take advantage of the RTL implementation, our multi-core platform provides the exact cycle count of the system. We adopted TSMC 0.13μm CMOS technology to synthesize the proposed multi-core platform at 100MHz as operating frequency. The area overhead of the proposed PE-to-PE Core is only 3.28% (19.2k gates) in a PE. Furthermore, the aggregate throughput of this platform is 952.64 Mbps. Our future works include 1) optimizing throughput and latency of LLC library, 2) finishing FPGA prototype, 3) improving platform architecture to a cluster-based processing element and 4) extracting more characteristics such as power, energy and memory behaviors to ESL design. We can try to use DMA to move data between the local memory and the PE-to-PE Core. Re-coding LLC library by assembly language may also useful. The most challenging cache coherence issues must be solved in a cluster-based processing element.