Abstract
This thesis presents two multi-way circuit partitioning algorithms for Field Programmable Gate Arrays (FPGAs). Both algorithms assume partitioning a large digital circuit into multiple devices of a single type (homogeneous FPGAs). The objective of the first algorithm is to minimize the number of required devices. It iteratively applies an extended and enhanced Fiduccia-Mattheyses based bipartitioning heuristic. The objective of the second algorithm is to minimize the delay of the partitioned circuit. It is based on clustering functional cones, and minimization of number of clusters and overlapped nodes by merging clusters and deleting nodes using delay information. Both algorithms produce promising experimental results over many existing partitioning algorithms.