Abstract
Analog-to-digital converter is the major intermedium of analog signals and digital signals, so the efficiency of analog-to-digital converter greatly affect the quality of the signal at the receiving end. However, with the rapid growth of data transfer volume and speed requirements, high sampling rate high-resolution analog digital converter for the impact on the resolution of overall signal receiving end is becoming much more crucial. In the thesis, the researches of multi-channel time-interleaved analog-to-digital converter are mainly mentioned which includes the non-ideal effects analysis of multi-channel and simulation results of multi-channel time-interleaved sampling switches. The back-end analog-to-digital converter will be introduced and divided into two parts which is successive approximation analog to digital converter and pipeline analog to digital converter discretely. A 10-bit 100MS/s SAR ADC with ENOB 9.92 and perfect DNL、INL. The average power consumption is 2.42mW and the average energy consumption is 25fJ each conversion. The circuit structure of pipeline analog to digital converter is mainly comprised of Flash ADC and switch-cap sub-DAC