Abstract
In this thesis, standard specification study, functional simulation, architecture definition, and circuit design along with FPGA implementation of the ECMA-368 [1] baseband transceiver for high speed and ultra wideband transmission with full digital synchroniza-tion is presented. A baseband transceiver with transmission rate up to 480 Mb/s is proposed and meets the highest transmission data throughput regulated in the standard ECMA-368. To reach such a high data throughput, a parallel-four signal processing architecture is adopted for this proposed baseband transceiver. The sampling frequency in the front- end of the proposed baseband receiver is 528 MHz. Therefore, the operating frequency of this proposed baseband receiver operates above 132 MHz. The proposed baseband transceiver includes several functional parts, timing synchronization, frequency synchronization, FFT, channel estimation, equalization, phase tracking and de-modulation. Most functional parts choose suitable existing algorithms to implement for the functionalities of themselves. However, a new signal processing algorithm is proposed for de-modulation. This algorithm combines a maximum likelihood detector, the dual carrier modulation (dcm) mapping rule, and some designer-made assumptions together. Four multipath models are quoted and ±40 ppm carrier frequency offset and sampling frequency offset are also added into the functional simulation of this baseband transceiver. Synopsis Design Compiler (DC) is applied to estimate the power consumption, the clock timing, and total gate counts for the hardware design of this baseband transceiver. The characteristic of the fast Fourier transform (FFT) and the inverse fast Fourier transform (IFFT) within this proposed baseband transceiver is the single-delay feedback architecture with parallel-four datapath. By some low power design techniques, the dual core FFT/IFFT consumes less power and less gate counts compared with others' design. In addition, some functional blocks of the proposed baseband transceiver are even verified by FPGA. The total power consumption of this baseband transceiver is about 489 mW and the area is about 420 thousand gate counts.