Abstract
This study utilizes TSMC 0.35um Mixed Signal 2P4M Polycide process, combined with proposed post-process to design and fabricate a CMOS-MEMS accelerometer. The merit of this study is that through post-CMOS process with wet, and dry etching to design and fabricate a symmetric layers stacking CMOS-MEMS accelerometer (with 4 metal layers and 3 dielectric layers) by metal via design on structures; Moreover, for the purpose of electrical routing using this post-CMOS process, a structure design at anchors for electrical isolation is proposed. The results show that overall device performances can be enhanced, ex. higher device sensitivity, thermal stability and reduced existent residual stresses in CMOS-MEMS.