Abstract
In this study we successfully demonstrate the silver-nanoparticles-catalyzed chemical reaction wet-etching for commercialize, single-side polished, orientation with (100) face, and 4-inch with diameter silicon wafers with regular and around 4 μm uniform depth surface large-scale patterned nanowires. And we already prove that there is the enhancement for the effect of stress distribution in the nanowires region, which means the structure of nanowires is able to enhance the strength for the silicon wafers. However, when we apply the nanowire structure into the silicon wafer for the semiconductor industry, there are chances that several kinds of particles generated from many procedures of semiconductor processes may be stuck in the voids between each nanowire, then resulting in the doubt for contaminations of instruments and instability of electrical performances. In this research, we try to deposit the protection layer which does not affect the electrical properties of silicon wafers and being compatible with the semiconductor processes upon the surface nanowires while the voids between each nanowire still exist to achieve the stress enhancement of the silicon wafers. Furthermore, the protection layer would be able to reduce the possibility for particles being stuck into the voids, achieving the effect of covered nanotexturing for applying to semiconductor industry.