Abstract
The serial advanced technology attachment (SATA) is becoming an important technique for internal storage interconnection. As the clock becomes faster, the electromagnetic interference (EMI) issue is harmful. The level of EMI can be mitigated with the help of filters, shielding and spread spectrum clocking. Spread spectrum clocking technique, based on a frequency modulation, has been the simplest and effective way. The frequency modulation alters the center frequency of the clock and spreads the power of spectrum over a broader range. This approach reduces the fundamental clock frequency EMI, as well as the harmonic components of higher order, decreasing the EMI radiation of whole system. A Spread Spectrum Clock Generator (SSCG) for Serial-ATA II is realized in this thesis by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable divider with little power consumption added. This Half-integer divider utilized a half division ration to have a small phase jump to reduce quantization noise. The SSCG achieves an output clock of 3 GHz and 4883ppm down spread with a 30 KHz triangular waveform and been designed based on TSMC 0.18μm 1P6M CMOS process. The rms jitter of spread-spectrum clock is 6.94ps.The EMI reduction is 13dB.The power is 12mW under 1.8-V.The chip area is 1090×1330μm^2.