Abstract
In a computer system, the speed of an embedded memory is usually a key factor of system performance. As the deep sub-micron techniques evolving, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to the access limitations. To solve the testing problem, BIST (built-in-Self-Test) circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. An access timing measurement unit of embedded memory is proposed in this thesis. It consists of a TDC (time-to-digital converter) with the BIST. Based on the dual-slope principle, the modified TDC can measure the maximum access time of embedded memory. The measurement range is designed from 1ns to 5ns. It can achieve the at-speed measurement with 50ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262x92 □m2 under 0.35□m 2P4M CMOS process. This measurement unit with the built-in-self measurement method can achieve both advantages of at-speed and accurate measurement for memory access time.