Abstract
First, we should claim that every layout and ring oscillator simulation report in the thesis is built by NTHU. This thesis focuses on the new FEOL and new MEOL confidential profiles. With the miniaturization of the technology, more and more confidential technology information should be protected. It is a critical issue that how to protect the confidential information and let other extraction tool can still extract circuit well. In the advanced technology, the transistor will be FinFET structure, and if we still want to use ASAM to extract the parasitic of MEOL then we have to reestablish the ASAM MEOL library again. Now the number of patterns in ASAM library is about 3000, but actually there are only half percentage of patterns we used. Besides, using the technology file can also protect the information of foundries, because the designers only have to know the parasitic capacitance and the resistance instead of the real profile or the characteristic parameters of the structures, and then they can use it to do the rest simulation. In previous tranditional technology nodes, the performance of the ring speed is dominated by front-end-of-line (FEOL); however, with the miniaturization of the technology, back-end-of-line (BEOL) becomes more and more important for circuit performance. It is a hard to reduce contact parasitic resistance in advanced process node. Hence the device designers must change the structure between FEOL and BEOL. They changed the profile from transistors to M1. Actually, they used M0-A, M0-B and M0-C instead of OD contact, and used M0-P and M0-C instead of poly contact they used before. We named this part of structure which above transistor and under M1 - MEOL. Since the structure has become more complicated than before, it’s important to analyze the parasitic effects in MEOL (it is independent of FEOL and BEOL) and can’t be negligible. The new advanced process nodes require the foundry to provide the designers with more DFM and statistical modeling service tools, for tremendous power, performance, and area advantages. The modeling and tooling flow services are with new challenges in such areas as lithography, variability, and complexity, resulting in optimization APR and verification re-synthesis, due to Layout-Dependent Effects (LDE) including but not limited to lithography, CMP, and stress. Huge sets of new, complex layout and manufacturing rules will pose an implementation and signoff challenge. With the interconnect density increases in the advanced process, a simple digital IC may content thousands of transistors. The extraction of the whole chip interconnect parasitic effects becomes more time consuming for 3D field solver. Therefore, the library based 2.5D solver is popular for designers to use. In the proposed program –ASAM(Accurate Software API for MEOL Modeling), it is library based 2.5D software which is designed to extract the parasitic parameters in MEOL. In the ASAM, it contains two parts - ASAM Library and ASAM extraction tool. When the parasitic parameters are found by ASAM, then these results will be combined in FEOL’s and BEOL’s LPE tools.