Abstract
在本研究中，我們在全球資訊網(World-Wide-Web, WWW)下建立一套全新 的晶片測試策略之經濟分析系統(The Improved Evaluation System for TEst Engineering Methodologies, ESTEEM2)，讓晶片或系統設計者可以 利用這套軟體選擇適合的測試方式。很多經理人認為可測試性設計( design for testability, DFT)是一種多餘的負荷，不管是在發展或是生 產的過程。然而我們的系統將全盤考慮時間及各種測試性設計的關係，並 顯示測試性設計可以縮短研發的時間，如此可以減少研發人員的薪資花費 、縮短上市的時間，並在整個產品生命週期內得到最大的收益。生產上的 花費也會因為測試時間的縮短而大幅縮短。如果經理人單純認為測試性設 計是一種晶片面積的額外負荷，他們最後會發現沒有測試性設計會花費更 多的預算，尤其是大型的系統及大型積體電路。我們的系統採用時間關聯 式預算估測，以及各種收益估測，這些可以有效幫助經理人預估不同的測 試性設計對降低預算、提高收益的影響。ESTEEM2系統是以C、mSQL及 Apache全球資訊網伺服器所建構而成。使用者可以利用一般瀏覽器來使用 本系統，如網景公司Netscape。我們同時還預建一些初始模型，不過，系 統允許一般使用者自行建立自己的模型。目前有兩個內建的示範電路預估 模組，一個是IEEE 1149.5 MTM-Bus僕模組晶片為主的個案討論，另一個 是LZ77硬體壓縮晶片的測試策略預估。每一位使用者可以自行拷貝這些示 範用模組內的模型，並調整其內部參數以符合自己電路之需求。這是一個 持續性的計畫，以後還有更有彈性、更完整的預算、收益及測試模型會加 入本系統。 In this thesis, we present the improved World-Wide-Web (WWW) version of theEvaluation System for TEst Engineering Methodologies (ESTEEM2),to aid decision making with regard to which test methodology should be usedto develop a VLSI chip or system. Many managers consider design for testability (DFT) to be an "overhead" for development and production cost.Our system, however, takes a full consideration on the relation between DFT and various time models. We will show that DFT mayactually help engineers to shorten the total time needed in product developmen, which leads to lower man-power cost and shorter time to market,and therefore results in more revenue through out the product's life time.Production cost may also be reduced due to lower testing cost. If managers consider only the area overhead of DFT, they mayfind that design without testability actually costs more,especially for VLSI chips and systems. Our system uses time-related cost and revenue models. It helps managers toevaluate different DFT methodologies to reduce overall cost and/orincrease overall revenue. ESTEEM2 is developed with C, mSQL, and Apache Web Server.The user access the system using web browsers such as Netscape.We propose cost and revenue models for default calculation, but user specified models are allowed. There is a built-indemo circuit --- an IEEE 1149.5 MTM-Bus slave module chip --- showingour proposed system parameters. Every user can copy this demo circuit to his own folder and adjust the parameters to meet needs.This is an on-going project, with more realistic and complete costand revenue models and test methodologies to be developed and included in the future.