Abstract
This study employs standard TSMC 0.18um 1P6M CMOS process to design and implement Pirani vacuum gauge. Generally, Pirani vacuum gauge consists of heater and heat sink units. The heat generated by heater is transferred to the heat sink through gas molecules whose thermal conductivity depends on their pressure. This study proposes a novel structure design to improve the performance of Pirani vacuum gauge which is increasing the thermal resistance of heater. By increasing thermal resistance, the heater can obtain higher temperature comparing to typical one under the same power heating. Therefore, the efficiency of heat transfer can be increased and further improve the performance of the gauge. This study presents two different structures to achieve the goal of improving the device performance without changing device footprint size. Firstly, this study presents a complementary inbuilt heat sink design. This design has the following advantages: (1) The hole in heater can increase thermal resistance of heater, (2) The inbuilt heat sinks compensate the lost active area, (3) The heating and sensing material is composed of metal, so there are no much SiO2 to influence the heat transfer, and (4) Easy integration with packaged CMOS-MEMS devices for pressure monitoring. Then, this study presents another complementary bump heat sink and cavity heater design. This design has the following advantages: (1) The bump heat sink vertical integrates with cavity heater increases the active area, (2) The cavity in heater increases thermal resistance of heater, and (3) Easy integration with packaged CMOS-MEMS devices for pressure monitoring.