Abstract
In this thesis, we propose a hardware implementation for a 512-bit RSA cryptosystem core using systolic array structures. Based on modified Montgomery's algorithm, the iteration required is half of the original Montgomery's algorithm and thus has some speedup. Besides, our circuit is also designed for the Chinese Remainder Theorem (CRT) technique. This can further improve the throughput with a maximum factor of 4 in the best case. The processing unit of the systolic array has 100% utilization because of using Block Interleaving ofmultiplication and square operations in the modular exponentiation algorithm. The number of clock cycles needed for a modular exponentiation is only 0.13M in the best case, and 0.24M in the worst case, assuming that we are dealing with 512-bit number. The critical path delay is only 6.13ns, so our design can achieve decryption rate of 578Kb/s and 328Kb/s in the best and worst cases, respectively. This design is suitable for decryption and digital signature.