Abstract
Although VLSI fabrications increase their requirement for product yield, the existing layout optimization algorithms for yield enhancement are ineffecient in circuit sensitivity measurement. Therefore, this thesis presents an analysis method to measure the layout sensitivity efficiently and accurately. The sensitivity of a circuit layout is analyzed by the Voronoi diagram approach. The time complexity for the proposed method is O (n) for the layout with n circuits. This sensitivity measurement is applied to three yield optimization algorithms to enhance their performance. The method proposed herein also provides further insight into the properties of the circuit layout. The technique for analyzing the sensitivity of circuits can be extended into other measurements. Furthermore, conventional optimization algorithms could employ this method to increase their execution performance.