Abstract
The paper presents a pipeline analog to digital converter (ADC) used for video applications. The 10-bit ADC has an input signal range of ±0.5 V with the resolution near 1 mV. Sampling rate is 100 MHz. To reach the high speed, low power conversion, ADC implemented with pipeline architecture. How to implement a high speed, high gain Opamp is the bottleneck of ADC design. The Opamp used gain boost and two-stage techniques. Gain boost circuit strengthen the DC gain of Opamp without reducing bandwidth. Two-stage can get wide input common mode range and wide output swing. Pipeline ADC can use this advantage to amplify the full-scale signal stage-by-stage and lower down the precision need stage-by-stage. This will help to save power consumption of pipeline ADC. With the aid of spice and matlab, the simulation DC performance of ADC claims no missing code, DNL within ±0.2 LSB, INL within ±0.5 LSB. The simulation AC performance of ADC claims SNDR are 60.6 dB@5 MHz and 50.2 dB@40 MHz. The total power dissipation of ADC is about 722 mW. The power reduction can be done using error tolerance of pipeline structure. It is predicted to reduce about 25% of power dissipation.