Abstract
The dynamic PLA style has become popular in designing high performance microprocessors because of its high speed and predictable delay. However, the wire delay has become a dominating factor in deep sub-micron design, and thus long wires in dynamic PLAs can cause a significant delay problem. This thesis presents an efficient and practical method to improve the timing delay of dynamic PLAs. Note that we are considering mask programmable PLAs. Therefore during the PLA design, unnecessary excess wire segments in a PLA can be removed. The removal of unnecessary segments of wires can improve the timing delay of a PLA. We have observed that the amount and the length of removable wire segments depend on the ordering of input/output/product lines. We proposed a force-directed reordering method to reorder the input, output and product lines, and then prune the excess wire segments to improve the timing of a PLA. We have conducted experiments on a large set of MCNC benchmark circuits. The results show that the timing delay can be further improved by 11.57% in 32 benchmark circuits after applying our technique.